> > Are you trying to calculate the file bits and physical address
> > from a 'linear' adress, for use on a pic-12? There are
> > much faster ways to achieve that once you allow
> > other relations between the linear and phyiscal addresses!

> Exactly. It's just I don't have previous experience in the subject.
> Could you point me in the right direction?

A short answer: when you move your pointer to the fsr,
exchange bits 5 and 7, so the bit that distinguishes between
the shared and the paged registers (5) was
the most significant bit of your pointer. This enables you
to do normal pointer arithmetic (a carry from the lower 4 bits will
affect the bank bits, not the shared/banked selection bit).

Wouter.

A longer ansewer which I will put on a web page sometime:

The PIC-12 uses a banked architecture to address the internal registers
(RAM).
The addressing scheme used is:

   < B: 3 bank bits > < S: 1 shared/banked bit > < O: 4 bits offset >

When an instruction specifies an address it specifies only the
S and O bits, the B bits are taken from the status register.
It is a major challenge for a compiler (or assembler programmer)
to avoid the need to change the B bits.

When an indirect address is used (FSR register) all
bits are taken from the FSR register.

In Michrochip terminology each bank (as selected by the 3 bank bits)
consist of a shared part (S=1) and a banked part (S=0).
The shared part always addresses the same registers,
independent of the B bits. The shared part contains the
hardware-specific registers (port buffers etc.) and a few (8)
registers that can be accessed independent of the current
value of the B bits.

When a pointer to a block of data must be manipulated the
addressing scheme choosen by Microchip becomes a pain in the ass.
Within each bank things are fine,
the pointer can be incremented, decremented etc. and it will
point to the next or previous register. But when a bank
boundary is crossed (the S bit changes from 1 to 0) the pointer
ends up in the shared part instead of in the next (or previous)
banked part, so without precaution a pointer can not simply be
manipulated and then used in the FSR to address a register.

What we need is a well-behaved pointer (+1 addresses the next register,
-1 address the previous). This can be achieved either by
- using a different reprentation for pointers than the one
envisioned by Microchip and / or
- using a different representation for +1 and -1.

My preferred option is choose a pointer representation that
has S as most significant bit:

   < S: 1 shared/banked bit > < B: 3 bank bits > < O: 4 bits offset >

Now any carry/borrow from the O bits directly affects the B bits.
When such a pointer is moved to the FSR the S bit must be returned
to where Microchip in their wisdom has put it. This is no big
deal but it requires a few assembler instructions.

Another option is
- to use < O: 4 bits offset > < B: 3 bank bits > < S: 1 shared/banked bit >
- to represent +1 and -1 by +16 and -16, and feed any carry back to the
lowest (S) bits. Now the move from our representation to
the FSR is a simple swap, but increment and decrement are
more difficult to implement.

I have not found any way to keep both the increment / decrement
and the transfer to FSR trivial.