Hi,

> Power supply bypassing - if your supply lines are long (1.5 to 2" can be
> long when using chips that are very fast) then you should put bypass
> capacitors (0.1 or 0.01 uF ceramics) on each chip's power supply pins.

This seems to be the favourite contender at the moment... I need to go out
and buy some caps by the sound of things. Incidentally, how fast is "very
fast"?... The PIC's drive by a 20MHz clock, but its internal instruction
speed is 5MHz, so the narrowest pulse I'll be delivering to any latch or
other external component is 200ns. Is that sufficient to cause problems?

> Ground noise - if your ground line is long and snakes around a lot, you
> can actually create enough voltage across its impedance (mostly the
> inductance) to cause transitions in your logic.  Bypass caps help a lot
> here, but you may need to rethink the layout.  Narrower traces have both
> higher resistance and higher inductance.  Power supply lines should be at
> least 0.020", larger if possible.

I'm doing everything on a protoboard so there are ground lines across the
board in 3 places. Any idea what these things are like as far as inductance
goes?

> Propogation and setup times - you don't say what your '574 and your '245
> do, but is it possible that if one changed faster than the other, you'd
> get problems?  The capacitance of your logic probe may change the slewing
> of the O3 pin, and thus change the relative timing of the '574 and '245
> outputs.

The 245's a transceiver used for reading PC parallel port outputs, and the
574 is a latch for sending data to the PC. The protocol's entirely
synchronous (driven by two external handshake signals) and doesn't rely on
them operating at the same time or speed, so I don't think that's the
problem.

> Glitches - if the A0-A3 lines all change at the "same" time, they may
> actually be some nS different.  The 'LS138 may be fast enough to create a
> "glitch" on one of its outputs when one of its inputs changes before the
> others.  The capacitance of the probe could have a significant effect on
> the amplitude and/or duration of such a glitch, whether it's on the O3
> pin or not.  A solution would be to set up all your addresses (A0-A2)
> first, then the enables (A3).  Then remove the enable, then change the
> address.  This kind of goes hand in hand with propogation and setup
> times.  What you want is to let the glitches happen but make sure that
> your logic ignores them.

I'm careful to use the EN line on the 138 so that none of the outputs are
enabled when I'm changing from one to the other... (although I freely admit
to a degree of inexperience about these things, I did think of the problems
this would cause!).

Thanks to everyone for all the advice I've received on this.

Cheers,

Ben