Ben - Basically, as Ansel said, you shouldn't be having either level or loading problems on any of your pins, unless "all the peripherals" is too much loading on the PIC pins, which isn't likely. I suspect you have other problems. As you seem (by your own admission) not to be an expert in electrical design, I'll point out a few things that could be a problem. Power supply bypassing - if your supply lines are long (1.5 to 2" can be long when using chips that are very fast) then you should put bypass capacitors (0.1 or 0.01 uF ceramics) on each chip's power supply pins. Ground noise - if your ground line is long and snakes around a lot, you can actually create enough voltage across its impedance (mostly the inductance) to cause transitions in your logic. Bypass caps help a lot here, but you may need to rethink the layout. Narrower traces have both higher resistance and higher inductance. Power supply lines should be at least 0.020", larger if possible. Propogation and setup times - you don't say what your '574 and your '245 do, but is it possible that if one changed faster than the other, you'd get problems? The capacitance of your logic probe may change the slewing of the O3 pin, and thus change the relative timing of the '574 and '245 outputs. Glitches - if the A0-A3 lines all change at the "same" time, they may actually be some nS different. The 'LS138 may be fast enough to create a "glitch" on one of its outputs when one of its inputs changes before the others. The capacitance of the probe could have a significant effect on the amplitude and/or duration of such a glitch, whether it's on the O3 pin or not. A solution would be to set up all your addresses (A0-A2) first, then the enables (A3). Then remove the enable, then change the address. This kind of goes hand in hand with propogation and setup times. What you want is to let the glitches happen but make sure that your logic ignores them. Hope this helps. Don