Michael Rigby-Jones wrote:

> You could use the EPROM method, you would either have to have several
> external latches for the addres bus or an external counter.  The
> disadvantage of a simple binary counter is that to move to a specific
> location in the memory, you would have to count up through all the
> previous locations.

  OTOH, if the PIC has nothing else of import to do, that's great!  This
application is obviously not speed-critical, or not particularly so.
For an application where serial access is the primary objective, you
*should* use counters rather than shift registers.

>  Or you could use a counter on the lower order bits and control the
> high order bits of the EPROM directly from the PIC and divide the
> EPROM into several equal sized partitions.

  That approach is appropriate to the elimination of a PIC.  If however
you want to *use* a PIC, use two (or more) counters such as (74HC)4040
with common reset and separate clocks.  That's three lines to control up
to 24 address bits.

  Maximum random access time at about 50 ms (by clocking both counters
at
once; 4095 counts at conservatively, 10 instructions per loop plus a
little) is trivial in this application (you might have to mute the
"tick" from the output).

  This could be relegated to a 12C508 with the ToC (Table of Contents)
vectors stored in the PIC rather than the PROM (note I said PROM to
match an OTP), or there are various ways to read the parallel data into
the PIC.

  Sounds like a nice cheap approach to me, but you certainly do have to
compare it to an ISD chip with *all* the functionality integrated.
--
  Cheers,
        Paul B.