I assume that the frequency is not fixed, in which case a simple delay
line won't help.

What kind of range of frequencies do you expect?

It is possible to make a clock multiplier using a device at a much higher
clock rate and then a PLL to divide as needed and sync up with the incoming
clock. Your resolution would be the ratio of the incoming clock to the
clock rate of the higher speed device.

>Actually, I'm still trying to figure out how to multiply a clock pulse.
>If I take my clock pulse, xor it with it's 90 degree retartded friend, I
>would double my original clock.

Clock multipliers using PLLs are used in some microprocessors to get
extra edges inside the chip for gating various stages. I don't know if
there are any single chip solutions to implementing a PLL based clock
rate multiplier, but it seems it should be possible to design one out
of available parts.

That is all assuming the incoming clock rate is low enough.

>
>Just can't seem to figure out how I'm going to get "more" out of
>something than what I'm putting in.