Tjaart van der Walt wrote:
> >   That's writes **AND READS**, not just writes.  With a
> > tight wait loop, you could probably run into that.  10
>
> I RTFM'ed, and you are perfectly right. It is a feature
> carefully hidden in one of the datasheets. Oh well.

  Yeah they do stress the "high endurance" a lot even though
it isn't exactly apples to apples vs eeproms.  But then
again they are superior for almost every other use..  Still
might even be the best thing for what you're doing, just
keep the read speed down a bit to make the life reasonable.
Only real question then is the stats on failure, is one
location likely to fail long before the others, or do they
all make it to 10B and then fall apart?
  About a year away, but at abcnews.com in the tech section,
Hitachi and Cornell U have apparently got something using a
transistor and a second transistor instead of cap like DRAM,
and got leakages etc down enough that it's NV.
Alan