Alan King wrote:
> 
> Tjaart van der Walt wrote:
> 
> > >   Hmm, I thought the other major drawback to these was that
> > > reads cause wear as well as writes.  May have been improved
> > > and not be a problem now, but at 50 MHz you could run into
> > > that wall if it's still there..
> >
> > They are rated for 1E10 write cycles! Walter suggested that
> > the SPI reads be done by the ISR in the background, so it
> > will interleave with the execution of it. I don't think
> > I'll be able to read the SPI at much more than 1Mbit/s.
> > Maybe even less.
> 
>   That's writes **AND READS**, not just writes.  With a
> tight wait loop, you could probably run into that.  10

I RTFM'ed, and you are perfectly right. It is a feature 
carefully hidden in one of the datasheets. Oh well.

I wondered why everybody wasn't using the technology....

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