Tjaart van der Walt wrote:

> >   Hmm, I thought the other major drawback to these was that
> > reads cause wear as well as writes.  May have been improved
> > and not be a problem now, but at 50 MHz you could run into
> > that wall if it's still there..
>
> They are rated for 1E10 write cycles! Walter suggested that
> the SPI reads be done by the ISR in the background, so it
> will interleave with the execution of it. I don't think
> I'll be able to read the SPI at much more than 1Mbit/s.
> Maybe even less.

  That's writes **AND READS**, not just writes.  With a
tight wait loop, you could probably run into that.  10
billion may not be that large if you're starting from the
100kHz+ range.  At 1 MHz reading one location that's 10,000S
or ~3 hrs before you are past their rating.  Spread across
10 locations for a tight loop and that's a little more than
a day.  Or even 100 for a small program (or the commonly
executed parts of a larger program) would have an even
better chance of one out of the 100 failing within 10 days.
And that's assuming that their guesstimate of 10B is
correct.  Wouldn't be too surprising if one out of the 100
died before that.  Even a 1k not looping program would only
get 100 days.  At first I was going to say that "Long as you
cache tight loops in the Scenix you should be ok, but it's
not indefinite use like RAM..", but after thinking about it
more that 1k hits hard.  That's not a tight loop, but you
can still expect it to fail in <6 months at 1 MHz.
Definitely not RAM!
Alan