Hello,

I am using the hardware Slave implementation of I2C. For some reasons, after
a slave-transmitter configuration,
the hardware doesn't reset the SCL and SDA lines as high impedance open
drain input, thus the master thinks the slave is stretching the clock here's
the code I use after testing the r/w bit in sspcon

this code is in the isr



        bcf     STATUS, RP0


        bcf     PIR1, SSPIF     ; clear interrupt bit

        movlw   'A'
        movwf   SSPBUF          ; data in buffer
        bsf     SSPCON, CKP     ;send data by relinquishing clock to high
        bcf     PIR1, SSPIF     ; clear interrupt bit

        btfss   PIR1, SSPIF     ; wait for next I2C interrupt to send next data
        goto    $-1

        bcf     PIR1, SSPIF     ; clear interrupt bit
        movlw   'B'
        movwf   SSPBUF          ; data in buffer
        bsf     SSPCON, CKP     ;send data by relinquishing clock to high
        bcf     PIR1, SSPIF     ; clear interrupt bit

        btfss   PIR1, SSPIF     ; wait for next I2C interrupt to send data
        goto    $-1

        bcf     PIR1, SSPIF     ; clear interrupt bit
        movlw   'C'
        movwf   SSPBUF          ; data in buffer
        bsf     SSPCON, CKP     ;send data by relinquishing clock to high

        btfss   PIR1, SSPIF     ; wait for next I2C interrupt to finish sending
data
        goto    $-1
        bcf     PIR1, SSPIF     ; make sure I2C interrupt clear before exiting


then exit from the ISR. However, once the master receives the data (which is
does fine), the slave keeps the SCL low.
Thus the master times out. What can I do?
Please somebody help me otherwise I will fail my class (sorry to sound
desperate but it's true).

Franck