> >
> > At 50 MIPs I think it could compensate for the fact that it will be
> > bit-banged.
>
> It will. However I don't think you'll get the full 10 to 15 Mhz available
> bandwidth bit banging.

A two or three byte cache and a software SPI would likely give
surprising performance on any processor using some form of
byte code interpreter.  This can be organized as the logical
equivalent to pipelining on a microcoded processor. (A new
instruction set is born) If the SPI is implimented as a interrupt
driven backgound task then fetches are interleaved with
byte code interpretation.

We have directly supported user defined memory devices
for quite a while in our products. Small buffers an offer a
termendous performance boost.

Walter Banks
http://www.bytecraft.com