Hmmm... Is CPLD an overkill for this app? My guess is you want 24 data
lines and x number of address lines, which can easily exceed 40 pins of
PIC. CPLD (or even FPGA) have many pins and most of them can be I/O.
Using VHDL, coding shouldn't be all that bad. Am I oversimplifying the
problem?

Try www.cypress.com for their CPLD kit. Comes with
"not-so-great-but-usable" book on VHDL as well as programmer kit for
$200.00 so you can start flashing logic devices for this sort of
application. Beware, though; their software has bugs which will throw
off the result even if your code is correct. I suppose this is true with
all products.

G'luck.

"William K. Borsum" wrote:
>
> Hello All:
>
> PROBLEM:        24-bit A/D converters have a serial output, which I need to fe
ed
> to a parallel input sRAM at fairly high data rates.
>
> I NEED:         a hardware solution that will allow me to have our main PIC (a
> '74) monitor and control the process, but not be directly involved in
> pipe-lining the data from the DAC to the sRAM.  The serial output stream
> has the usual start, stop, ack and other over-head bits associated with
> either the I2C or SPI protocols, and the conversions are often driven by
> the SPI clock from the host device.  I wouldn't have a problem dedicating a
> small PIC to the process, but would probably need at least 28-32 ports to
> handle all the output data lines, SPI interface, and status and control to
> the "host".  Clock rates approaching 100KHZ are expected on the serial lines.
>
> If you have done something like this--even for 8-16 bit wide transfers--I
> would appreciate hearing from you.
> ****************************************************************************
> ********
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> text.
> Please note our new address and phone numbers.
>
> William K. Borsum, P.E.
> DASCOR
> P.O.Box 462885
> Escondido, CA 92046-2885
>
> V&M&F)  760-796-7785
> Direct)         760-796-7788
> <borsum@dascor.com>