Hello Franck.

>In setting up the I2C mode on a 16c73a for a slave, the TRISC bit for the
SDA and
>SCL line are configure as input; also the corresponding PORTC latches are
cleared.
>However when I check with a scope, I found out that these open drain
collector output a voltage
>(+5V) on the bus masking the signal from the master.

May be my experience will be helpful for you.

I found a similar problem too. I used another bits at PORTC as a
bidirectorial i/o. When bidir pins direction changed (by bit manipulation
instructions with TRISC register) the unwanted change of SCL and SDA pins
directions occurred. This is due the Microchip mistake in PORTC schematics.
In old data book (1995) there is no relations between input pin state and
results of bit manipulation instructions. By my opinion this is correct
design. But real silicon has another design. It showed in new data book
(1997). If port bit configured as a special function (particularly as I2C
slave) the results of bit manipulation with TRISC unpredicted! I workaround
this problem by use copy to TRISC instructions in place bit manipulation
instructions.

Michael Evstafiev