Hope I'm not repeating what someone else has already suggested but-

How well bonded are the earths between the control board with the failing IC
and the FET driving the pulse transformer. Any earth potential rise at the
FET end could cause the output of the IC to exceed its max (or min) limits
causing latchup and failure. If the cable is longish or there is any sort of
inductance or signal coupling in the earth loop then this could create a
damaging situation - particularly with the power levels and risetimes likely
to be occuring in the environment.

Note that the earth return inductance will not need to be very high to
generate substantial voltage from the high di/dt values you're likely to
find in this area. (V=L * di/dt) If L=1uH I=500A in 1uS then V=500V & more
significantly perhaps E=1/2 * L * I^2 = 125mJ = more than enough to do
damage!

My reccommendation would be to move the driver IC down to the same PCB as
the FET and drive it from a differential signal, rather than the single
ended one shown. Standard RS485 driver / receiver ICs might be an option.

The differential receiver would need to have a good common mode performance
but this is not too hard to arrange with even just a "long tail pair" of
transistors and a constant current source.

Alternatively, isolate the FET driver from the logic using an opto isolator
and keep the earths and supplies separate.

The other replies with respect to bypass diodes and series resistors should
also help but I'd look carefully at the return path impedance and coupling.

Richard
(rprosser@swichtec.co.nz)


From: Kelly Schauf <k3jsch@MAIL.GMTCOM.COM>


>To the forum:
>
>The problem I have does not involve a PIC; however, there appears to
be
>an abundance of knowledge in this forum regarding electronics based
on
>some of the messages I've read so far.
>
>Is there anyone out there in the forum that has experience with
Design of
>Experiments (Taguchi-type) in addition to their electronics
>troubleshooting skills.  I have been seeing repetitive problems with
a
>MM54C14J Hex Inverter (an old ceramic-style part) where the Vcc is
>getting creamed.
>
>Because the explanation of the failure will be a bit too long to
>adequately put into a message, the best place to get further details
of
>the failure type is to go to
>http://web.gmtcom.com/~k3jsch/sixsigma/access.htm
>
>The problem occurs regardless of the following:
>
>1) Whether it has been in service for only a few hours or at least
8000
>hours.
>2) Whether it is operating at a temperature of 55 degrees C or
slightly
>past 100 degrees C
>
>3) Whether it is operating in a 60Hz domestic unit or a 50Hz
overseas unit.
>
>4) date code of IC
>
>Any suggestions, etc., are welcome.  What I am trying to do is set
up an
>experiment at our production facility to inject noise, etc. into the
>design as it is running.  Factors I am looking at are :
>
>1) Levels of noise voltage to inject into the cable between the
>microprocessor unit that this IC resides on and the gate firing
board of
>the SCR bridge that is directly mounted over the 3-phase, 6SCR
bridge
>that ultimately runs either the left track or right track motor.
>
>2) Brand name of chip.
>
>3) Whether or not modification to the shielded cable and/or its
placement
>in the circuit would make a difference.
>
>
>Regards,
>
>Kelly Schauf
>k3jsch@mail.gmtcom.com
>