Justin, I know your mention of hardware is actually for the switch to generate an interrupt but, would you consider a NAND gate latch setup? Or is this too much or unnecessary hardware? I've build a sample circuit like this before but I've never tested its resiliency with a range of switches that have varying debounce times. Any information I've gathered from this approach has not pointed to this being a "better" solution. Unfortunately, I need this to be as robust as possible and with the solution being through software, I could at least "tune" the debounce if switches are chosen outside a comfortable range. I'm in the investigation phase right now and I'm using some simple SPST, normally open, momentary switches - I will ultimately move this to a setup that is rubber keypad/PCB contact assembly, for which I really appreciate the note from Paul Webster on switch/key design - that was great. -DO > -----Original Message----- > From: pic microcontroller discussion list > [mailto:PICLIST@MITVMA.MIT.EDU]On Behalf Of Justin Crooks > Sent: Monday, April 12, 1999 3:53 PM > To: PICLIST@MITVMA.MIT.EDU > Subject: Re: Newbie Toggle Switch Woes > > > I find this to be overkill. I design the hardware to interrupt on > keypress. I start the timer, and when the timer is done, I read the > keypress. I use a keypad that gurantees debounce time <10 ms, which makes > life about as easy as can be. I then wait until the key is definitely > released before allowing another to be read. About as simple as can be. > > I guess it depends how robust your application needs to be... adjust your > code accordingly. > > ---------- > > From: Andy Kunz > > To: PICLIST@MITVMA.MIT.EDU > > Subject: Re: Newbie Toggle Switch Woes > > Date: Monday, April 12, 1999 10:00 AM > > > > >Anybody have a favorite debouncing scheme? > > > > I use TMR0 to debounce. I only test the switch after "n" TMR0 > overflows, > > and only count the state as changed after it has been consistently in > that > > state for "y" times. > > > > You want to set it up so you get at least 3 samples over a 10-30mS > period. > > > > Andy >