Dwayne Reid wrote:

> Take note that TRIS works ONLY on ports RA, RB, RC.  It will NOT work
> on ports RD or RE.

  For that relative minority who use parts which *have* those ports! ;-)

> Taken from page 157 of Microchip document DS30234D (16C6x family)

> Since TRIS registers are readable and writable, the user can directly
> address them.

  And isn't that an example of doublespeak?  (BS)  Should read "the user
can *in*directly address them".  I consider the TRIS instruction direct
access; you simply use it to write W into the register without any
concern regarding RP0, RP1 etc.

  Most applications would spend the vast majority of time in Bank 0,
would they not?  That is after all, where the ports, timers, and many
important control registers are, are they not?  (Just looking at figures
4-7, 4-8 on page 24 of DS30390D).

  Furthermore, there is much to be said for making code which accesses
bank 1 (etc.) "critical" and disabling interrupts during such code, for
a much cleaner (faster) IRQ service.  (Extension: use bank 1 GPRs only
for interrupt service.)

  The TRIS registers have been classed as "unimportant" and I submit
that access to bank 1 is in fact, quite IN-direct.  I think that the
allocation of the TRIS registers in this bank makes for a very pretty
diagram, but is in fact a design bungle.
--
  Cheers,
        Paul B.