Gerhard Fiedler wrote:
> that's the 597, and if i read that data sheet right, it has got the same
> problem with cascading as all shift registers: it changes its output on the
> same (the rising) edge as it samples the input, which leads to a possible
> timing violation of the data hold time at the serial input. which may work
> or not, depending on the numbers of butterflies awake in china :)  since
> the min. data hold time for the serial in is usually much lower than the
> max. propagation delay shift clock to serial out, it probably works more
> often than not, but it still feels shaky...
>
> or am i wrong here?
>
> ge

Gerhard, you made me think, and looking at the circuit function, it
looks
like that the shift out bit follows the same timing from the internal
shifting Q = Q - 1, so, it means, that when clock goes up, Q copies the
(old and stable) state from Q-1, but the internal propagation is lazy
and it takes time to set Q = Q-1, so Q-1 state does not propagate to Q+1
at the same raise clock pulse.  Happens the same at the last shifted
bit,
the shift out. It means that when you clock up, the serial in of the
chip
#2 will just copy the actual (old) state of the shift out chip #1, and
then it will update the latches.  First all cells gate Q=Q-1 then the
real update happens. If this works internally, will work externally too.
Now, am I wrong here too? :)
--------------------------------------------------------
Wagner Lipnharski - UST Research Inc. - Orlando, Florida
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