>Surely the crystal load specification refers to the overall capacitance
>as seen across the crystal terminals? Since the caps at either end of
>the crystal in this type of circuit are effectively in series, then the
>capacitance seen by the crystal is:
>
>C = (C1*C2)/(C1+C2)
>
>which for the common case where C1=C2 becomes: C = (C1)/2
>
>So that for a 20pF crystal one would be looking at maybe 33pF each end?

|Interesting question. I've always used the method I described, and
|attributed any adjusting that had to be done to board, chip, and stray C.
|I've not seen a hard description from an xtal mfgr that really spelled it
|out either way. You could be right though.

I just had an odd thought... if what matters is the capacitance
across the crystal (at least once the thing is running) then it
would seem that using a circuit like this:

           .----XTAL------.
           |              |
OSCOUT ----+--C1--+---C2--+--- OSCIN
                  |
                  C3
                  |
                 Gnd

with C3 much larger than C1 or C2 (e.g. 10:1) would be about the
same as having C3 shorted, **BUT** it would be possible to see
and measure the differential current in C1 and C2.  Since any
differential current between C1 and C2 has to be returned through
the ground lead, it would seem like minimizing that would be the
goal, and a setup like the above would provide an easy way to do
that.

Note that if the PIC is programmed with something like:

        movlw   254
        tris    PORTB
Loop:
        bsf     PORTB,0
        bcf     PORTB,0
        goto    Loop

the edges of PORTB would make it possible to determine whether the
signal on C3 was in phase with OSCOUT or OSCIN; this in turn would
indicate which cap (C1 or C2) should be made larger/smaller.

How does that sound for an idea?