>can you eventually explain in a more detailed what the criterias are to
>optimize the oscilator circuit regarding emittation ?
>
>Which harmonics will be visible in which case ?
>
>Kind regards
>
>        Stefan


Odd harmonics are the worst. Most digital stuff is square waves, and as
Fourier showed us, they consist of all the odd harmonics. I take each
crystal frequency, and scan each odd harmonic up to 1GHz with an Icom
R-8500 receiver. The FCC tests you from 30-1000 MHz on radiated noise.

To keep the oscillator quiet is really very simple.
Use the right loading caps. This also means that your xtal will be "singing
the right tune"
Connect the caps at the crystal, and run a single track back to the uP
ground pin.
Don't dump it into a plane, and don't let anything else use this track.
Make the crystal tracks paralell, as short as possible, and as close to
each other as possible.
I also route exclusively with curved traces, which limits the impedance
discontinuities at corners. This is a real small effect, but curved tracks
are free, so I just do it.

The worst EMI to track down is a poor ground path.  Usually your micro is
feeding other chips, and each time it changes state on an output lead, the
input capacitance on some remote device is charged or discharged. This
means that there is, in the first moments, some appreciable current flowing
from the micro out to this remote chip.  That current MUST return to it's
source. In fact it WILL, and you'd better control which path it takes.
Planes would be fine if you had a plane layer with no holes in it, but in
the real world, your plane may have large holes in it, and you don't want
the return current having to run around a large hole in the plane (can you
spell ANTENNA?)  Run a fat track from every peripheral chip that's driven
by the micro, back to the micro. Then you can plane the rest, knowing that
you have assured a low Z path back to your micro.

NEVER NEVER NEVER put a cap on a signal lead to ground "to make it quiet".
All you're doing is forcing the driving chip to draw MORE current to
achieve the transition, plus that current is also dumped into the ground
system, and it's got to go somewhere.. If you absolutely must, you can add
a series resistor to slow down the edges. This should be done as close to
the driving chip as possible, usually 120 ohms will be good. You don't want
to make the edges too soft. This has to be verified with a scope in each
case, to make sure that you aren't violating any timing specs. It's a
viable option for distributed clock lines, or other fast signals that must
be sent around the board.

Power:  Each chip should have a bypass cap, located at it's ground pin.
Power runs from the chip's power pin(s) to the cap, and from the cap to
system power bus.  The "gridded" layout you see so often is a total
disaster. Think about what happens when a chip on a grid draws power.

It's all about current, and in every case, this rule applies:  PUT IT BACK
WHERE YOU GOT IT FROM.