Vincent Deno wrote:

>I am currently in the process of implementing a design which will be using
>four 74HC165s daisy-chained, all on the same clock line.  Unlike your
>design, all 4 will be on the same board which is approximately 2"x7".
>
>Unfortunately, there is little/no room for additional chips so "playing it
>safe" and using your fix is really not an option.  I was wonderng if it is
>likely I will run into a similar problem or must I rethink the design?
>
>Thanks,
>Vince Deno
>

My design involves ten 74HC165s each fitted on separate PCBs with a total of
about 15 feet of interconnecting cables.  The extra capacitance of the
cables, no doubt, added to the problem of clock skew.  It is surprising that
the data sheet doesn't specify a figure for maximum rise time of the clock.
As a result, there seems to be no way of knowing whether a particular
circuit will work or not until it is built!

You could use a single PNP transistor (configured to source current from the
5v rail) or FET alternative rather than a buffer IC to clean up the clock
pulses - the objective is to obtain a sharp low to high transition by
driving from a low output impedance source.

Perhaps the alternative 4021 shift register would be less fussy than the
74HC165 (being a slower logic family)?

The other idea is to run each shift register in parallel rather than as a
daisy chain.  Each could be clocked separately using a different PIC pin or
they could share the same clock line and you could enable each IC in turn
using the "Clock Inhibit" pin.  In addition to the requirement for extra PIC
outputs, this approach would also involve extra inputs to read the data out
of each chip.  I think that you could use a 4052 Dual 1-of-4 data selector/
mux to save some PIC pins (but, of course, this involves an extra chip).

Let us know how you get on ...

Regards,
Doug