Douglas Reid wrote:

> I am rather dubious of Paul's suggestion to clock each board one at a
> time by adding gates to introduce delays.  Surely ALL boards must be
> clocked at the same time otherwise data would be lost?   Paul wrote:
>>  You need to ensure no SR is clocked *before* a later one (in the
>> chain).  The best way to do this is to make sure earlier ones are
>> actually clocked *later*.

  You appear to have a different concept of "early" and "late" to mine!
To my mind, "early" means an input which must travel a longer path to
arrive at the end of the SR, not one which *arrives* before the others!
That given, I am sure the wisdom of my suggestion will be clear.

  Evidently this has not been necessary in your case.  Fine.
Interesting to note that a 74HC14 provides "stiffer" buffering than a
PIC pin which is rated to sink/ source 25/ 20mA, but ... so be it!

> The Schmidt trigger feature on the input may not be that important -
> however, it should help to ensure that multiple clock transitions are
> not generated even if some noise is present on the input.

  That's certainly what they make them for, though many of us like to
use them as oscillators! ;-)

> interestingly, MC68HC11 output impedance is listed as 1000 ohms (when
> driving high)/ 250 ohms (when driving low).  Thus the HC chip may give
> a 20 x improvement in output impedance and will presumably also
> greatly reduce the rise time of the clock edge.

  Hey, we're talking PICs aren't we?, not Woosy chips!

> An alternative idea (which I haven't tried) may be to use a pull-up
> resistor to "help" the PIC drive the clock line.

  No way JosŽ!  Not with PICs.  I know TTL logic used pull-ups in places
but that was s-l-o-w.  One trick was to use pull-ups to "help" TTL to
achieve CMOS logic levels.  The IÓC bus uses pull-ups, which is why you
must be extremely cautious using it outside its intended application of
on-PCB communication.

  The big limitation of pull-ups is that a 1 k ohm pull-up will only
contribute 500 µA to keeping a line above 4.5 V (on a 5 V rail) but will
source 5 mA when ypu have to pull them low.  PIC port B pull-ups (weak)
are special - they are current sources (I think).

> The data sheet for the 74HC165 does not mention the importance of a
> fast clock rise time.  Does anyone have a figure for the maximum
> acceptable rise time?

  Bottom of page 3.  http://www.st.com/stonline/books/pdf/docs/1911.pdf

  But I'm not sure how critical this is.  Ringing is more likely to be
a problem, so I'd go back and check termination, even if it works now!

> If I was starting again on this job, I might keep all the 74HC165s
> together on the one board and wire the switches back to this board.
>  This approach might be more sensible than routing the signal lines to
> each remote board.

  Pragmatic perhaps, but I tend to see the ability to distribute the
layout as the great advantage of the SRs.  I would think that some
applications may justify an extra 74HC14 on each board buffering (two
series gates each) latch, data and the clock so that all boards can be
completely daisy-chained with the last board going *to* the master and
the clock propagating *back* from that master (i.e., buffered on every
board).

  Of course output boards are daisy chained with the clock *following*
the data.  Neat!

> The drawback is slightly more wires needed - ie. 9 (8 switches plus 5v
> - assuming pull-up resistors located on remote boards)

  No, you do *not* put the pull-up on the remote board.  That's another
principle, all input should be ground-referenced, so no short to ground
can short out the power.
-- 
  Cheers,
        Paul B.