>Douglas Reid wrote:
>
>> My problem is in using multiple 74HC165s in a chain.  I am
>> experiencing bizarre behaviour in that changing a parallel input pin
>> level can affect the level read from another of the parallel inputs.

Thanks to everyone that offered suggestions.  I have now solved the problem!

Paul Webster gave me the clue.  Paul wrote:
>  The likely cause of this problem is a shifting error caused by lack
>of clock coherence.  Ignore the "load" line for the moment.

Paul is certainly correct in that it was clock skew that was causing the
problem.  Each of the 74HC165 has it's clock pin connected in parallel (all
driven from a single PIC pin, to answer Paul's question).  However, each
chip will have a slightly different logic threshold, resulting in each being
clocked at a different time on the rising clock edge.  Interconnecting
cables will add capacitance which slow down the edge of the clock signal,
compounding the problem.

I am rather dubious of Paul's suggestion to clock each board one at a time
by adding gates to introduce delays.  Surely ALL boards must be clocked at
the same time otherwise data would be lost?   Paul wrote:
 >  You need to ensure no SR is clocked *before* a later one (in the
>chain).  The best way to do this is to make sure earlier ones are
>actually clocked *later*.

Surely by clocking a board, it's most significant bit would be shifted out
into the least significant bit position of the earlier (ie. nearer to the
PIC) board - thus losing the LSB in that chip?

Dave Vanhorn wrote:
> Take slow, add series resistors at the drivers, say 120 ohms

I agree with Paul that this is NOT the solution.  After giving the matter
some thought, I came to the conclusion that I had to SPEED UP the clock
rising edge.  The faster edge will reduce the differences in time between
each chip being clocked.

I found the solution to be quite simple.  I added a 74HC14 hex buffer
(Schmidt trigger input) between the PIC and the clock line to all the
74HC165s (only one gate of the buffer being used - ie. all IC clock pins are
still being driven in parallel).  The HC buffer has a low output impedance
of approx 50 ohms which will have improved the rise time relative to direct
driving by the PIC pin (I wonder what the figure is for the PIC pin output
impedance?).  This has solved my problem!

The Schmidt trigger feature on the input may not be that important -
however, it should help to ensure that multiple clock transitions are not
generated even if some noise is present on the input.

I have a book which compares output impedances of different logic families.
4000B is as high as 800 ohms (whether driving high or low) and,
interestingly, MC68HC11 output impedance is listed as 1000 ohms (when
driving high)/ 250 ohms (when driving low).  Thus the HC chip may give a 20
x improvement in output impedance and will presumably also greatly reduce
the rise time of the clock edge.

An alternative idea (which I haven't tried) may be to use a pull-up resistor
to "help" the PIC drive the clock line.
How much current can a PIC output sink when the output level is low?  This
would determine the minimum value of the pull-up.

The data sheet for the 74HC165 does not mention the importance of a fast
clock rise time.  Does anyone have a figure for the maximum acceptable rise
time?

If I was starting again on this job, I might keep all the 74HC165s together
on the one board and wire the switches back to this board.  This approach
might be more sensible than routing the signal lines to each remote board.
The drawback is slightly more wires needed - ie. 9 (8 switches plus 5v -
assuming pull-up resistors located on remote boards) compared to 6 (5v, 0v,
clock, load/shift, data in, data out) per board.

Thanks again for everyone's help and I hope that my experiences can save
other people time when using multiple shift registers!

Regards,
Doug