Tom Handley wrote:
>
>    Eric, typical SRAMs have !CE (Chip Enable), !OE (Output Enable), and
> !WE (Write Enable). You can connect both SRAMs to the same bus but to read
> from them you have to bring both !CE and !OE Low. To write, you have to
> bring both !CE and !WE Low. In your case, I would tie !CE Low and select the
> appropriate !OE and !WE lines.
>
An alternative way (still uses 4 pins) is to have common !OE and !WE
going to both SRAMs and an individual !CE for each device.  This method
has the advantage of using only one more pin for each additional SRAM if
you ever need to modify your design.  When using parallel EEPROMs,
disabling CE puts the memory into a lower current standby mode (saving
battery life) - I don't know if this holds true for SRAMs.

--Matt