Michael Rigby-Jones wrote: > The last place I worked used some very strange decoupling caps. They were > fitted underneath the IC, without using a socket. They were very thin with > the same outline as the IC and thin pins that could be pushed through the > same holes as the IC. This got around the problem of long leads with the > socket type decouplers. > > Regards > > Mike Rigby-Jones > mrjones@nortelnetworks.com The company that does those is CCI: http://www.cci-msc.com/ They also make some nice bus bars for board stiffening and power distribution. Unfortunately the last time I looked at their Micro-Q caps (several years ago), they were prohibitively expensive. If you were to use more than a few of them per board, it was more cost effective to add a power/ground plane and a good bypassing structure to the pcb. However they are very good if you've already got a noisy design that has to be fixed; less expensive (in the short term) than a redesign. In response to other topics in this thread: Its also important to remember that the clock frequency is usually not the frequency that determines the design point for your power distribution system. The rule-of-thumb is: design frequency = .3 / rise time Where the frequency is in Hz, and "rise time" is the fastest switching speed in use in your circuit, in seconds. So at a rise time of 2.5ns (not uncommon) the frequency you should be designing your bypassing for is 120 MHz (even if your PIC is just ticking along at 4 MHz). (Note that the ".3" ranges between .3 and .5, depending upon whose thumb you are using.) The positioning of bypass capacitors is a popular subject, and a good place for information on it is at Howard Johnson's web site: http://signalintegrity.com , where the subject has been addressed several times in his newsletter: http://signalintegrity.com/news/1_6.htm http://signalintegrity.com/news/2_3.htm http://signalintegrity.com/news/2_1.htm http://signalintegrity.com/news/2_26.htm This reprint from PCB Design Mag is good too: http://signalintegrity.com/articles/straight/bypass.htm Note however, that I believe in all instances these discussions regard pcb's with full power and ground planes; the recommendations there may not be applicable to 2-layer, wire-wrap, or proto-board layouts. This is also a popular subject on the signal integrity mail-list, (subscription info at http://www.qsl.net/wb6tpu/si-list/info.html ), and in its archives at http://www.qsl.net/wb6tpu/si-list/ (Threads on this list are often addressed in Johnson's newsletter.) Gary Crowell