Dwayne, I'm using an ispLSI1016E-100LJ which is a 100MHz 44-pin PLCC device. It costs around $6-$7 in single quantity. It's hard to explain the device's resources without having studied the architecture. It includes: 32 I/Os 4 Dedicated Inputs 3 Clock Inputs 1 Global Reset shared with one of the clock Inputs 1 Global Output-Enable shared with one of the Dedicated Inputs 2000 Gates 96 Registers 16 Generic Logic Blocks (GLB) Again, there is more to it. Those resources are arranged in GLBs or Generic Logic Blocks. They include several options such as hardware XOR gates, OR gates, product term Resets, Output-Enables, and Clocks. Each GLB includes 4 registers which can be configured in several ways. There is also a `High Speed Bypass" option to route product term outputs directly to the output macrocells. Output macrocells can be configured in a variety of ways such as Inputs, Outputs, Latched Input, Bi-Directional with or without Latched Inputs, and 3-State. Programming them is really trivial with just a 5V supply. The Lattice software to do this is free. The download cable uses a 74HC/LS367 and a few passives. Most folks already have the parts in their `stash'. I want to emphasize this as I've got very little response which means folks are either not interested or `turned-off' by the use of a CPLD. This really is easy and cheap. I provide the isp-Stream file for the Lattice software. All you do is download to the chip (assuming you build the download cable and download the free software). Using an external clock is an interesting idea but there is no room left to implement an internal divider. I've decided to release the parallel and serial versions which provide more capability. I've tested a 20-Bit serial version with a 20-Bit address and an up/down counter. You can use the counter or load it from a shift register for random access. This would be a dedicated SRAM controller, no chip enables, and would require a 28 or 40-pin PIC. I may be able to add an internal divider but the timing would be crucial and both the divider and standardized serial software would have to provide for different clock rates which would be very difficult. The possibility of things geting out of sync is very high and I would'nt trust it... Also, it only saves 1 pin and requires more software overhead than simply shifting Bits out a pin. To build the Lattice download cable, see my web page at: http://www.teleport.com/~thandley/Wilbure.htm For more information about Lattice Semiconductor's products and to download the ISP Daisy Chain Download software and/or ISP Synario design software, contact: http://www.latticesemi.com - Tom At 07:39 PM 1/6/99 -0700, Dwayne Reid wrote: >Tom - I've been following your adventures with the Lattice PLDs and SRAM >memory addressing with considerable interest. Its one of those projects >that I would very much like to have spent some time with but haven't been >able to so far. > >I'm curious as to which Lattice PLD you are using (part #, number of >macrocells, etc)? What does it cost? > >I'm still of the mind that PLD code very tightly coupled to a SPECIFIC pic >serial routine would give the best bang for the buck in terms of pin count >and speed. This would be based upon the serial clock being derived from >OSC2. If the divide network was held in reset until the pic asserted the >enable line, it should be possible to keep the whole thing down to 2 or 3 >lines. In other words, write a nice fast serial i/o routine, figure out how >many OSC2 cycles it requires per bit, then build that divider into the PLD. >It should work! > >Amyways, I'm eager to see how you make out. Best of luck! > >dwayne > > >Dwayne Reid >Trinity Electronics Systems Ltd Edmonton, AB, CANADA >(403) 489-3199 voice (403) 487-6397 fax