|   I have an update to my SRAM and Chip-Enable Controller that would use
|serial data instead of 8 data Bits to load the SRAM Address latches. This
|would require more overhead but cut the number of PIC I/Os from 12 to 6. Add
|to this !Read and !Write lines. This would also increase the latch from
|19 to 24 Bits. For example, a 16F84 could control a 512KByte SRAM with 8
|I/Os. The following is the revised host interface:

With regard to your earlier question about how to handle active-
high vs active-low signals, I think 99% of memories out there are
going to be active-low.  What you could do to be safe would be to
have the chip select pins float until their polarity is established
and then let the user supply pull-ups or pull-downs as appropriate
to establish the "idle" case.

Otherwise, I think the idea of a serial interface for SRAM is a nice
one, though if you're going serial it might be good to push for
a pin-count reduction to either five pins (one clock + 4 data,
allowing pretty good transfer rates) or two/three.  I don't know
how many internal latches and such your chip gives you, but one
approach I've been thinking would be very nice for a 2-wire serial
bus would be for the CPU clock signal to be one of the wires (the
capacitive loading of the PLD input would have to be taken into
account, but that shouldn't be a problem).  If this was done, only
one PIC pin would be needed to access memory, and the accesses could
be done very quickly [writes could occur at one bit/three clocks and
reads could occur at one bit/two clocks].  Does that sound at all
interesting?


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