|Can you detail why this would be a problem with larger PICs (multiple code bank
s)?

>How about this version ?
>
>       org     4
>       Int                       ;  Interrupt Handler
>
>       bcf    INTCON,T0IF        ;  Reset the Interrupt Source
>
>       incfsz Counter_Low, F     ;  inc low
>       goto $+2                  ;  normaly skip incrementing HIGH-byte
>       incfsz Counter_High, F    ;  inc high on roll-over
>       nop                       ;  high is rolled over
>
>       retfie

|This may have a problem with a large chip with multiple code banks.  But
|for a small chip like the '84, you'll be just fine.  I have used precisely
|this method in a '558, so I know it works.

The "goto" is performed in a context where PCLATH is not known.
On the smaller parts (2K or less), PCLATH is not relevant for
the GOTO/CALL instructions; on the larger parts, it is.  One
approach to solve this problem is to "clone" the ISR at address
$0804 (and on 8K parts $1004 and $1804 as well) so that a GOTO
will find either the proper target (if PCLATH happens to have
its high bits cleared) or a "mirror" of it which will behave the
same way.

Too bad that AFAICT no C compilers for the PIC support automatic
cloning, since that could sometimes save many cycles in ISR hand-
lers, esp. when ISR's may have to nest (e.g. consider on a 20MHz
PIC with two interrupt sources: a timer which hits every 240
cycles and whose handler takes 120-200 cycles to execute, and the
PSP whose ISR only needs to take about 12 cycles but which should
manage to get in those 12 cycles within 10us.

If cloning is available, or if the code fits entirely within 2K,
the ISR can start with something like:

ISR:
                btfss           STATUS,5
                 goto           RP0WasClear
                bcf             STATUS,5
                btfsc           PIR,?   ; PSP interrupt flag
                 goto           DoPSP1
                movwf           T2IntWSave
                swapf           STATUS,w
                iorlw           2               ; Set RP0 flag in saved STATUS
                movwf           T2StatSave
T2IntMain:
                bcf             PIR,?   ; Tmr2 interrupt flag
                bsf             INTCON,7        ; GIE -- Allow other interrupts
                ...

RP0WasClear:
                btfsc           PIR,?   ; PSP interrupt flag
                 goto           DoPSP0
                movwf           T2IntWSave
                swapf           STATUS,w
                movwf           T2StatSave
                goto            T2IntMain

DoPSP1:
                movwf           PSPIntWSave
                swapf           STATUS,w
                iorlw           2               ; Set RP0 flag in saved STATUS
                movwf           PSPStatSave
                goto            PSPIntMain
DoPSP0:
                movwf           PSPIntWSave
                swapf           STATUS,w
                movwf           PSPStatSave
PSPIntMain:
                ...


Not exactly elegant, but at least stuff will get saved in the
right spots.  If it's necessary to save PCLATH before checking
what caused the interrupt, then that location will have to be
copied somewhere else before interrupts can be enabled (and of
course, saving PCLATH will require saving W and probably STATUS
as well... rather a lot of work).