Adrian, I designed an SRAM controller for the PIC16C74A/77 using a
Lattice ispLSI1016E CPLD. It requires a chip-select, 8 data lines, and 3
state-select lines. I use RE2, Port D, and RA0-2. It provides 19 address
lines and 5 external chip-selects or latch-enables. It supports 32KB, 128KB,
and 512KB SRAMs in a standard 32-pin socket. The 1016E comes in a 44-pin
PLCC package.

   The first 3 states load the address latches. The other 5 states provide
chips selects and latch-enables for expansion. I'm about done testing this
and I'll put it on my web site when it's finished. I also have a Lattice
ispLSI CPLD programmer that can be built for free depending on what folks
have in stock. I provide the isp stream file.

   I had originally built this in support of my PIC-based logic analyzer
which is in prototype. I decided to make a versatile proto board using
microEngineering Labs' PICProto64 board. The board has a 40 pin ZIF socket,
the 1016E CPLD, a 32-pin SRAM socket, a 74C922 keypad encoder, MAX232A
RS232, an SPI-style interface, and an LCD interface. There are a variety of
jumpers to configure all the peripherals. I'll also put that on my web site
when it's done. I'm testing it right now with the CPLD.

   - Tom

At 03:39 PM 12/20/98 +0000, Adrian Gothard wrote:
>At 11:45 20/12/98 , Mark J Anstice wrote:
>
>>I have a (common?) question.  I need to interface a PIC with a RAM chip.
The
>
>I do this with a 16C74 (has a uart) to a 128kbyte SRAM though it has enough
>i/o lines to address a higher capacity part.
>
>Regards
>
>Adrian
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