On Tue, 8 Dec 1998, Harold Hallikainen wrote:

>         I'm thinking of just using a couple 8 bit serial in parallel out
> shift registers to drive address (and maybe control lines) of the SRAM,
> and using 8 bits of I/O on the PIC.  Serializing the address lines could
> save a lot of pins.  Tristating the data lines could allow them to be
> used for some other purposes (reading switches through resistors or
> something like that).

Actually using a CMOS counter will be faster (1..2 x 4040) but makes
jumping backwards complicated (long live caches and structured
programming w/o subroutines).

I have used a combination of these on occasion (high 14 addresses from
4040, low 4 direct from micro).

It is possible to use a serializer for the data too, but it makes it very
slow and CPU-intensive. I think that a PIC 64 is what is needed. It can be
used to address a large device and still have pins left. (I used such a
PIC for similar purposes). The C64 has enough oomph to drive even a 32
MB SIMM with some time left over, and some pins left over.

I might also mention that a HCT373 or two can be used to reduce the data
and address IO pin count to 8 using 8031-style ALE-latching. Only 1 strobe
pin is required (the latch devices are in series and supply addresses only
to the target SRAM). Addressing is pretty fast under the circumstances.

If one uses 'Ohm' type gates <G> on the memory D I/O then only 2 wires are
required to control the device with up to 64k x 8 and this is in range for
a F84. One control wire supplies the strobe pulses to the address latches,
and also drives the CS of the RAM (to allow bus muxing if req'd), the
second is wired directly to ~WE on the RAM.

2 IO pins remain free for general use (serial ?).

hope this helps,

Peter