The SX already has ADD/SUB with C (it can be enabled or disabled)...



> -----Original Message-----
> From: pic microcontroller discussion list
> [mailto:PICLIST@MITVMA.MIT.EDU]On Behalf Of Morgan Olsson
> Sent: Sunday, November 08, 1998 2:47 PM
> To: PICLIST@MITVMA.MIT.EDU
> Subject: Upgrade instructions! WAS Re: PIC versus Scenix
>
>
> At 12:56 1998-11-08 -0800, you wrote:
> >While designed to be comatible with the 5x series PICs, there are
enough
> >differences speed-wise: 1 clock/instr., bigger stack, jitter-free
> >interrupt, etc that they could be considered completely different.
The
> >programming spec is different and allows in-system programming by
using
> >the oscillator pins instead of port I/O's. Internal hardware has also

> >been added to allow in-system debugging in your own target board -
> >you'll never need a bond-out emulator again! All interrupts are
> >jitter-free. From the above features, the software structure can be
> >considered more RTOS-ish, and the possible uses for the SX only start
at
> >PIC replacement - there are many applications a SX will fit into that

> >have never been considered for an 8-bit MCU before!
> >
> >With all this in mind, I would consider the SX completely different.
The
> >only similiarity is the instruction set/opcodes.
> >
> >Stephen Holland
> >scholla@ibm.net
>
> Is it also exactly the same binary instruction coding?
> It seemed like Starfires compatible gizmo had a convert utility.
> Maybe they have new interesting instructions? =)
>
> I have always wondered why Micrichip wasted silicon and
> instruction codes on
> CLRW    ( = ANDLW 0 )
> NOP     ( = BSF or BCF unused/unimplemented bit )
> TRIS    ( = MOVWF  (Mchip recommends not to use TRIS no more anyway) )

> OPTION  ( = MOVWF  (Mchip recommends not to use OPTION no more anyway)
)
>
> Removing this useless crap would make room for a few more usable
> instructions instead (without needing more instruction bits or
silicon).
> So, probably (i don4t think they are stupid) they have implemented it,
or
> will implement it soon.  (Like there were undocumented instructions in
Z80
> and 6502)
>
> What i have in mind:
> ADD / SUB with carry in.
> Selectable inc/dec of FSR when read/write INDF
> Theese would probably speed up a lot of math considerably!  :)
>
> Manufacturers, are you listening?
>
> ...While you are listening: i want another FSR/INDF... with inc/dec of
FSR
>
> Compatibility: If we don't use the new instructions we just run the
> generated old-style code from the usual assembler/compiler through a
> converter, like for Starfires CPU.
>
> Using the new instructions would of course need a slight change in PIC

> compiler and simulator, but that would not be too hard.
>
> /Morgan
>         Morgan Olsson                   ph  +46(0)414 70741
>         MORGANS REGLERTEKNIK            fax +46(0)414 70331
>         HDLLEKES           (in A-Z letters: "HALLEKAS")
>         SE-277 35 KIVIK, SWEDEN               mrt@iname.com
> ___________________________________________________________
>