Actually you are only allowed about 5% relative error between the two
ends as you can only get 1/2 a bit out (not one whole bit)  before
you are sampling in the wrong bit - the sampling starts in the middle
of the 1st bit after the leading edge of the start bit and must still
be inside the correct bit when the sample for the last data bit
arrives, 8.5 bit times later.

(1/2 bit) / (8.5 bits) ~ 5.8%


regards


    Russell McMahon

>If you are using standard asynchronous serial with 10-bit frames
>(1 start bit, 8 data bits, 1 stop bit), then your cumulative clock
>mismatch for both ends can be almost 10% and still work correclty.