At 08:43 AM 1/09/98 -0600, you wrote:
>Because I am not versed in the complete specs and such of the moto 68HC711E9
>device, and perhaps someone is, is there an equivelent to this in a pic?
>I've got an old design that uses one, and for both cost and packaging
consideration,
>I'd like to know if first the device match, and second, is there a translator
>anyone has written to convert moto assembly to PIC assembly.  I don't have the
>time or inclination to write one or convert, unles (HINT), Microchip wants to
>steal some business from moto and do this for me.  The moto comes in a 52PLCC
>and I would rather have some SSOP device.
>
>

For a start the E9 has 8x8 bit ADC, something like 10 bidirectional I/O
lines 10 output only and 4 input only lines. Some of these I/O lines are
mixed across one port. The E9 has 12K of internal EPROM, 640 bytes of EEPROM
and 512 bytes of RAM, and a 32 byte register page. Is any external memory in
use? If so how much and what for. Other functions offered by the E9 are an
SCI and and SPI port, an a TIMER with input capture and output compare (5 of
these but all on the one timer and connected to porta (Still very good though))
As for the software bit! You will have to try again. Your programmer has
preferably mapped the register pager down to the first page, and set the
internal RAM to overlap, and placed the stack into the second ram page
(Upper 256 bytes). This would have been done to reduce the code size and
increase the run time speed. While this is only a minor point, the E9 has an
extensive addressing scheme that allows for many forms of linear addressing
in the entire 64k von Newman architecture, whereas the PIC (Like the good
old 8051) is a Harvard architecture. The interrupt structures and latencies
are also very different, as the E9 will store all working registers before
entering the interrupt. Also the E9 will only process one interrupt at a
time i.e. Unless the "CLI" instruction is used on the condition code
register, interrupt will halt all processing until complete. The E9 also has
an RTI, this is non maskable (Like the external NMI it has and one external
interrupt pin too) and is often used to control task scheduling. The E9 will
nest subroutines up to the size of the stack RAM (divided by 2 of course).
These are only some of the problems, many others involve the hardware (Most
are easy to overcome).
Without knowing or seeing the application, or seeing the software I can not
offer a definitive answer. If you care to tell me more I will see what I can
do, then a possible PIC chip can be looked at.


Dennis