Hi Dominic (Dominic Gualtieri), in <35B82191.E2748CF3@networx.on.ca> on Jul 24 y
ou wrote:

> I was wondering If anybody on the list knows how to make a phase lock
> loop using a
> Pic. Thanx in advance.

Something I've done on an AVR S1200 (I've combined it with 3-to-1 majority
receiver).  It's a simple DPLL that can be done in a _very_ few lines of
code:


Read the comparator output regularily, ie 7x per bit interval.  You then
get 7 readings per bit.

0011111 1100000
....... .......
   ^       ^

The marked location ^ is the received bit.

After determining the received bit, you scan the 7 slices for bit changes.
In the above example there are some, so you are not in sync with the
sender.

To adjust your phase, insert an 8th slice, or drop one (only 6) for the
next bit interval:

0011111 1100000 00111111 10000000 1111111 0000000
....... ....... ........ ........ ....... .......
   ^       ^        ^        ^       ^       ^- no bit changes -> 7
 normal   normal  8 sl.     8 sl.  no bit change -> 7 slices

As you can easily see, at the end you're in perfect sync with the sender.