I'm using the PIC16c73a  to do a PWM on CCP2 and a compare on CCP1.  I'd

like to use the clear on compare mode (with timer1), but when I write
0x09 to the CCP1CON, the pin(RC2) is cleared on _that_ instruction.
Actually, on the 3d clock phase relative to when pin writes usually
occur.  The code works fine in simulation mode.  The problem occurs in
silicon.

Here's a (stylized) snippet of my code:

    bcf    timer1enable
    clrf    tmr1L
    clrf    tmr1H

    movlw    comparevalue
    movwf    ccpr1L
    clrf    ccpr1H

    clrf    ccp1con
    bcf    pir1,ccp1IF
    movlw    ccp1modecontrolbyte        ; 0x09
    movwf    ccp1con

I've verified that each of the registers tmr1L, tmr1H,ccp1con,pir1,
ccpr1L, ccpr1H all contain the correct value after writing to them.  I
know there is an errata about timer1 registers sometimes inadvertently
incrementing.  The appropriate pin _is_ set up as an output.


If I try the pin SET on compare mode, by writing 0x08 to CCP1CON, the
compare works perfectly over the whole range of possible compare
values.  This is with exactly the same code otherwise.  I've also tried
different initialized pin states, to no avail.

Any suggestions?.  I have the errata for rev B silicon dated 11/96.  Is
this related to the #2 errata about the CCP special event trigger on
compare?  Is there a newer errata?  Does anyone have any simple code
that I can compare my code with?

I've passed this problem on to the Microchip rep in Chicago, but they
seem to be rather busy although they promised to look at it.


Paul