Lattice has recently released a version of Synario and their fitter that
will support their larger CPLDs. This is a six month evaluation copy. I'm
going to redesign the logic analyzer to fit into one CPLD (probably an
ispLSI1032) instead of three 1016 CPLDs. I'm not starting from `scratch' as
the redesign will mainly reduce some external wiring between the three CPLD
version.

  The current state of the design supports up to 32 channels expandable in
groups of 8, 32K Bytes of storage, a 24-Bit trigger comparator, and a
programmable post-trigger counter. The maximum sample rate is 40Msps. Sample
rates vary from 40Msps to 10sps. The post trigger delays are fixed at 1, 16,
64, 256, 1024, 4096, 16384, and 32767 Bytes. You can select 3 clock sources;
external, internal clock divider, and a host software clock. The last 2 can
be used to clock the circuit under test. There is an option to transfer 4 or
8 Bits at a time.

   The new version will require 1 Lattice CPLD that includes everything
except the SRAM, probe buffers (74ACT574s) and SRAM data buffers (74HCT244s)
to support 4 or 8-Bit transfers. All of the configuration is handled by a
2-wire serial interface. I designed this to support both a PIC and a PC host
with a `legacy' parallel port. In the 4-Bit transfer mode it requires 15 I/O
lines and 19 in the 8-Bit mode.

   I'm going to look into increasing the trigger comparator to 32 Bits and
increasing the memory size from 32K Bytes. Multiple trigger levels was
suggested earlier but that would require several CPLDs as I would need to
duplicate the trigger comparator for each level. The comparator uses a lot
of pin and macrocell resources. This is not a simple equality comparator. It
provides for individual Bit don't-care states and it's configured by buried
shift registers.

   You can easily add a DSO module with 8 Bits of resolution, 32K storage,
and up to 4 channels. This requires an external analog front-end with
trigger circuitry and an A/D converter. I've run several SPICE simulations
on a DSO front-end mainly based on Linear Technology, Maxim, and Analog
Devices op-amps. In all versions, there will be at least a 50Mhz +/- 1db
bandwidth for a sampling rate of 40 Msps. The DC performance should compare
with existing commercial products. The phase margins have varied quite a bit
but I consider this a low priority for this project. The input impedance and
capacitance will be compatible with standard scope probes (1Meg/20pf).
Obviously it will be up to the user to ensure proper layout/construction
techniques. However, I need to first concentrate on the basic logic analyzer
which is at the core of any DSO add-on.

   The following is the current three CPLD host interface which should be
very close to the single CPLD interface:

   SCLK  - Host Serial Configuration Clock. Active-High.
   SDI   - Host Serial Configuration Data.
           Host sends 60 Bits of data, MSB-first. This includes:
             Clock Polarity (Active Edge).
             Clock Source (Clock Divider, External, or Software).
             Clock Divider Prescaler (40Mhz OSC, /10, /100, /1000, /10000,
                                                 /100000).
             Clock Divider /5, /4, and /2 Enables.
             Post Trigger Delay (1, 16, 64, 256, 1024, 4096, 16384, 32767).
             Trigger Bit Qualifier Enable (24 Bits).
             Trigger Bit Qualifier (24 Bits).
   FSWR  - Software Clock source.
   RCLK  - SRAM Read Clock. This line is held Low during Capture. When you
           read SRAM data, host software clocks this line on the rising edge.
   INIT  - Initialize analyzer for each sample capture. Active-High.
   ARM   - Starts the Capture mode. Active-High.
   STOP  - Manually terminates the Capture mode. Overrides Automatic mode.
           Active-High.
   READ  - Sets Read mode. Active-Low.
   S0    - Read Control State select:
   S1    - "
   S2    - "
           This provides the SRAM 74HCT244 data buffer chip selects.
           There are 8 in the 4-Bit mode and 4 in the 8-Bit mode.
   WRITE - This is a control signal that you monitor to determine when the
           Capture mode has terminated. When this signal is Low, the Capture
           mode is active. The host software determines the relative
           trigger address given a 32K circular buffer and the known
           post-trigger delay.

   MODE  - This line is tied Low for 4-Bit transfers and High for 8-Bits.

   - Tom