>     A few bods have mentioned that they are annoyed by the way in which a
>     large number of micros divide down the external clock, resonator or
>     crystal usually, and run instructions at that speed ....
>
>     What are the reasons for people finding this so distasteful? I
>     understand that clock division and PLL circuits can be noisey, but I
>     get the feeling that this is not the only reason.

Annoyances:

1. Greater EM emmissions, making it harder to get FCC certification,

2. Greater power consumption, which is a problem for battery-powered devices,

3. More attention has to be given to careful oscillator design to get
accurate clocks,

4. Slower processing rates given a maximum clock speed,

and just for the principle of it,

5. The perception that all those clock cycles are being "wasted".

I designed a TI DSP-based battery-operated consumer device, and the DSP ran
at 20MIPS from a 20MHz clock, one instruction per clock cycle. This was
directly beneficial to each of the points above.

Stephen.