>
>I'm not at all sure on the newer processors, but from a historical
>standpoint, most of the old designs needed several phases of clock for the
>internal registers and so on.  Like ACC to memory buffer to memory buss to
>memory, needing three phase changes just to move data from the ACC to the
>memory.  I know, bad example, but the last time I really worked on anything
>like that was 15 or so years ago.  The clean way, was just  a higher speed
>external clock, and build your 8 phase (or whatever) sq wave from that.
>I'd almost bet the current crop of micro's do the same thing internally,
>depending on the design team.  After we get by the real hardware "why" of
>the clock, then we can look at the marketing thing and be properly amazed
>at their insights.  (cheep shot at the marketing types and the folks that
>believe them).
>
>
>
>'Grif' N7IVS


True fact.. Some of them needed 50% duty cycle as well, and the only way to
insure that is to divide the clock once more.

When you add a few clock phases, you're up to clock/8 in no time :-P
Now your osc 3rd and 5th harmonics are up 8x higher, and it puts you
in a fair bit more trouble than you needed to be, especially if the layout
isn't spectacular.

Current draw has to be higher than it otherwise would be, which makes
more heat, EMI, and just plain costs more watts to run.

Of course bad code can also have a huge impact on the picture. I recoded
one system, and took the clock from 12.288 (which was beyond the part's
max!)
to 3.575, did the same job, and even had a little time to spare.