At 05:20 PM 7/9/98 GMT+0200, you wrote:
>Hi,
>
>>      A few bods have mentioned that they are annoyed by the way in which a
>>      large number of micros divide down the external clock, resonator or
>>      crystal usually, and run instructions at that speed ....
>I think one disadvantage of a clock divisor is that it limits the
>maximum frequency at which a part can operate.  Take the good old 8051
>for instance.  It has a /12 and therefore to have it run at an
>instruction clock of 5MHz, you have to clock it at 60MHz!  Even if it
>could be clocked at 60MHz, it would be a non-enjoyable execise to build a
>good 60MHz oscillator and it would consume a large amount of power.
>
>A further implication is EMC.  With EMC laws becoming stricter, it
>becomes more and more important to limit the highest frequency in your
>design.  If you need a 24MHz oscillator to get the same performance from
>a 8051 than you would get from a 2MHz AVR (maybe even 1MHz), then the AVR
>would be a far better choice on EMC considerations alone.
>
>Just my 24/2 cents worth...
>Niki>


I'm not at all sure on the newer processors, but from a historical
standpoint, most of the old designs needed several phases of clock for the
internal registers and so on.  Like ACC to memory buffer to memory buss to
memory, needing three phase changes just to move data from the ACC to the
memory.  I know, bad example, but the last time I really worked on anything
like that was 15 or so years ago.  The clean way, was just  a higher speed
external clock, and build your 8 phase (or whatever) sq wave from that.
I'd almost bet the current crop of micro's do the same thing internally,
depending on the design team.  After we get by the real hardware "why" of
the clock, then we can look at the marketing thing and be properly amazed
at their insights.  (cheep shot at the marketing types and the folks that
believe them).



'Grif' N7IVS