Pavel, my goal is to provide the core logic and supporting hardware
design for the logic analyzer. Then I want to release it to the public in
hopes that the software becomes a group effort. While I want this to be a
PIC project I'm also designing it to be compatible with a PC host using a
parallel port. I am also looking at using a 16C76 or 16C77. The host
interface requires 15 I/Os in the 4-Bit transfer mode and 19 in the 8-Bit
mode. One issue is the time it takes to transfer up to 128KBytes of data
to a PC for each sample.

   If you are using the ispLSI1032, then you must have the full version of
the Lattice fitter and Synario. I only have the starter kit. It would cost
around $2500+ to upgrade. It's hard to justify the expense for a
vendor-specific product line even though Lattice is local here in Portland
and I've been using their products for around three years. I could easily
put this in a 1032... The design could still be shared as the Daisy Chain
Download Software is free. I'm providing the JEDEC and ISP Stream files in
addition to the schematics. Note, I'm avoiding getting specific in certain
aspects of the schematics such as the pod buffers as there are a lot of ways
to do this and I want to leave that up to the users.

   I had to `jump through many hoops' to fit as much as I did into three
ispLSI1016's. If I went to a 1032, I would start over taking the custom
modules that I designed and providing better integration. For example, a lot
of the configuration is handled by an SPI-style serial interface with shift
registers in all three chips. So two chips have SDI, SDO, and SCLK lines
while the remaining chip has SDI and SCLK inputs... Several shift register
outputs use external pins to connect to the other chips. Still, it replaces
dozens of 74xx `glue' logic...

   As far as testing, I only have the functional waveform test in Synario.
The Timing Analyzer is only included in the full version. I've ran
functional tests on the ABEL modules and the top-level schematics as well as
static tests on the chips. That's a long ways from the `real-world' though.
I'll probably release the preliminary design before I actually build my own
prototype.

   - Tom

At 05:08 PM 7/8/98 +0200, Pavel Korensky wrote:
>At 06:13 8.7.1998 -0700, Tom Handley wrote:
[snip]
>>   I've designed a PIC-based 32-bit logic analyzer that uses several Lattice
>>macros and 3 ispLSI1016's. I still need to finish the documentation but it's
>>been on hold until I catch up on other work like my garden ;-)
>
>:-)) It seems that I am trying to reinvent the wheel. Is your analyser the
>commercial product or is it possible to download the schematics, firmware
>etc.
>I am trying to build the analyser for my own bench because all commercial
>solutions are too expensive.
>I downloaded the PCLA schematics (by D.L.Jones and D. Bulfoni) from web and
>I started to adapt the ispLSI chips (basically trying to fit as much as
>possible into one isp1032 and reduce number of ispLSI chips to one). I am
>also trying to add the 16C76 control to the whole thing, mainly because I
>would like to have serial communication with analyser.
>If you can share the design, I can stop the effort and return to other
>projects (which I should finish asap, but which are currently pushed on
>stack). :-)
>
>
>Best regards
>
>PavelK
>
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>* Pavel Korensky                                                         *
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>* SUMMA SCIENTIA - NIHIL SCIRE                                           *
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