-----Original Message----- From: Gary Patterson To: PICLIST@MITVMA.MIT.EDU Date: Thursday, July 09, 1998 1:43 AM Subject: PICs and battery-backup SRAM >Hi, > >I've got an application where I want to use a large capacity, low power >SRAM along with a PIC controller. The SRAM will be used to hold data >and I want to use battery backup to protect the contents of the SRAM, >should someone accidentally disconnect the power supply from the circuit >etc. See below... > >Can somebody help me with 2 questions? > >1. What circuitry is necessary to implement battery backup for an SRAM? >2. If the PIC is writing to SRAM when the power goes off, how do I >ensure that invalid data isn't advertently written to the SRAM? > >I am using PIC I/O lines to directly control the address/data/control >lines of the SRAM. What SRAM You are using ? You wrote about "large capacity sram" - what size? Do You think about using Flash against SRAM? Flash not needs any backup battary, but have more writing time (~5-7 uS). This all about 0.5-N megabytes capacity, if you are not need so much, and not need small memory access - mind about serial eeprom (for example - if you want 128kbyte then 4x24LC256 is not more expencive then 128K SRAM and need only 2 PIC's pins). ================================== Alex Torres, Kharkov, Ukraine (exUSSR) E-Mail: altor@geocities.com 2:461/28 FidoNet Home Page: http://www.geocities.com/SiliconValley/Lab/6311