Hi Roberto and all,

At 19:10 1/07/98 -0400, you wrote:

>I'm designing an acquisition card (and other purposes) with a 12 bits ADC
>and a FIFO (CY7c344).
>A 16c74 drives the ADC and generates the clock to write data into the FIFO.
>An external device generates the clock to read data from the FIFO.
<snip>
>Sometimes 1 or 2 bytes (on 255) are lost reading the FIFO and sometimes the
>Empty Fifo signal is not read correctly.
<snip>
>The Cypress FAQ says slow transition can generate troubles, the clock
>rise/fall time should be about 3 ns!

 On a design that I've done, for a "long word UAR" (as one common UART,
but with 768 bits and without transmit section) and working at 10 Mb/sec,
I had the same troubles that you comment; the Empty signal, at some random
time, gets "crazy" and you start to retrieve un-entered data :-(.

 I tried a lot of things, to cover the transitions times also that the
Reset timmings were followed, without sucess. I used a AM7204 (AMD) driven
by a Xilinx CPLD (XC9536), and on the Read and Write lines, I was having
a very fast but important "undershot" (1.4V, with about 4 cm of track
length!!!), and a fall time about 2 nSec.

 I placed a series resistor (82 ohms), on the FIFO Read and Write lines,
to minimice the undershot, and the FIFO started to work 100% Ok :-).


 Best regards:

--
Roberto Deza Asensio        |  rdeza@unav.es
Universidad de Navarra      |  rdeza@cun.unav.es
Data Procesing Center       |  rda@cpd.unav.es