Hi Piclisters!
Sorry for the OT, but I'm becoming crazy :-(
I'm designing an acquisition card (and other purposes) with a 12 bits ADC
and a FIFO (CY7c344).
A 16c74 drives the ADC and generates the clock to write data into the FIFO.
An external device generates the clock to read data from the FIFO.
Now I'm working with a PC+digital I/O card (DIO24 National) simulating the
external device.
Sometimes 1 or 2 bytes (on 255) are lost reading the FIFO and sometimes the
Empty Fifo signal is not read correctly.
It's not a speed problem, this occurs also working step to step.
The problem seem to be random apart from it's occurs often when there are a
data transition from 0xFF to 0x00.
The Cypress FAQ says slow transition can generate troubles, the clock
rise/fall time should be about 3 ns!
How can I change my signals gradient?
Now I use TTL or HCMOS inverter but they aren't enough.
Any suggestion?
Please, send your answer directly to my work e-mail
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     rmarchini@facet.it
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there is already too many OT-traffic on this band :-)

Thank you very much for the attention and sorry for my bad english :-)

Roberto Marchini