> I understand a micron is one millionth of a metre.  When people say,
> "The Pentium uses a 0.35 micron process", etc, what does that mean?

For every process there is a set of layout design rules which specify
minimum dimensions, spacings, etc. for every layer in the circuit - 0.35um
would be the smallest dimension allowable in the circuit - typically a
transistor (MOSFET) gatelength or the minimum width of a metal track.

> What is 0.35 micron?  Is it the minimum width of circuit tracks?  Is it
> the area covered by a transistor?
>
> How many micron do our PIC's use?  How many micron were the first
> commercial chips?

Dunno about PICs.   I think the 4004 was made on a 10um technology and
that was 1971, I suppose earlier devices were even bigger.

> And some other mysteries while I am here :
> Who decided that the 74LS00 would be a quad 2-input nand gate, and for
> the rest of the series?

Dunno.

> Why does using a smaller micron process make a chip faster and draw less
> power?

Smaller is faster because all the capacitances and resistances are reduced -
you've got smaller devices, so smaller parasitics and shorter wires because
everything is closer.   You can also make a chip faster by throwing more
transistors at it as the area per gate will decrease as the square of the
minimum dimension - i.e. going from 0.5um to 0.35um can allow a doubling of
the number of transistors in the same area.   The power reduction comes from
a combination of factors - lower voltages are commonly used (though this will
slow the chip).   Also, for a static CMOS gate, power is used when the gate
is switching, charging up or discharging whatever capacitance is connected to
its output, this load will be reduced in a smaller dimension chip and so the
power consumption will be less.

ATB,
Aidan.