At 08:40 20.6.1998 +0200, you wrote: >>Hmm, problem is,that there is a lot of other interrupts, some of them >>should be as precisely timed as possible. On the processor with normal >>architecture, like Z80(accessible stack in main memory) is not a problem to >>write reentrant interrupt service or there are several interrupt vectors. >>But on PIC it is impossible. > >Your original question has already been solved, I guess, but regarding >nested interrupts - although I did not try it yet, IMHO reentrant interrupt >is possible, of course limited by stack and other resources. To preserve >status and W registers, you have to dedicate more memory and still there >will be short moments, when interrupts are disabled. Well, Sinclair is a >different beast... ;-) Nice idea... I will try to think about reentrant interrupts on PIC. It should work with simulated SP in memory. PavelK ************************************************************************** * Pavel Korensky * * DATOR3 LAN Services spol. s r.o. * * Modranska 1895/17, 143 00, Prague 4, Czech Republic * * * * PGP Key fingerprint: F3 E1 AE BC 34 18 CB A6 CC D0 DA 9E 79 03 41 D4 * * * * SUMMA SCIENTIA - NIHIL SCIRE * **************************************************************************