Martin Green wrote:

>      Tjaart, I know what you meant to say, but in you first paragraph you talk
>      about collectors and emitters and then link them to Vdd and Vss, when you
>      meant to say Vcc and Vee. Of course, it is with CMOS technology that the
>      drain and source of the CMOS transistors leads to the terms Vdd and Vss.

No, I didn't!

Here I linked the collectors and emittors to Vcc and Vee...

> In TTL (transistor-transistor logic) chips, the technology is based on
> bipolar transistors. Since you connect the Collector of a NPN transistor
> to the positive side, and the Emittor to the negative side, the chips are
> marked with Vdd for positive, and Vee for negative (ground)

...and over here I linked the drain and source to Vdd and Vss.

> In CMOS (complementary metal oxide silicon) chips, the technology is
> based on field-effect transistors. You connect the Drain to the positive
> side, and the Source to the negative side, hence Vdd and Vss.

Did I understand you wrong?

--
Friendly Regards

Tjaart van der Walt
mailto:tjaart@wasp.co.za

Add your voice !!
Vote at the Great G Com Public Vote. Go to :
http://www.wasp.co.za/~tjaart/gcomvote.html

|--------------------------------------------------|
|                WASP International                |
|R&D Engineer : GSM peripheral services development|
|--------------------------------------------------|
|SMS mailto: 0832123443@wasp.co.za  (160 chars max)|
|     http://www.wasp.co.za/~tjaart/index.html     |
|Voice: +27-(0)11-622-8686  Fax: +27-(0)11-622-8973|
|          WGS-84 : 26¡10.52'S 28¡06.19'E          |
|--------------------------------------------------|