Message-Id: 15504_ha5kfu From: ha5bwh@ha5kfu.#bp.hun.euro (Istvan, Retaller) To: piclist@mitvma.mit.edu Date: Tue, 16 Jun 98 21:47:09 EDT Message-Id: <15@ha5bwh.ampr.org> From: ha5bwh@ha5bwh.ampr.org To: piclist@mitvma.mit.edu Subject: How to program GALs Hi, everybody, Pavel and Alex asked me to tell more about GAL programming, but others also may be interested. Here are some notes to start. I know that there are obscure points, but I had even less information to start. I want to let the pleasure of invention to you. Things described here, are adequate to build a GAL programmer, but you have to work hard. Perhaps there are missing details, but this is what I want to tell about this topic. The infomations presented are written by my best knowledge. No intentional misleading was written, however, different manufacturers and different GALs may be programmed utilizing different methods. (E.g. I was unable to handle AMD's PALCE 16V8, while for Lattice, SGS, and NS it has worked.) ------------------------------------------------------------------- If you have any note, please, use my personal email address, I subscribe piclist occasionally and now subscibtion is off. ------------------------------------------------------------------- Let's clarify some things: You may find the internal structure of GAL's in most GAL manufacturers' databooks. Both the 16V8 and 20V8 consist of 8 OLMCs (=Output Logic MacroCell). The inputs of these OLMCs are connected to a matrix's horizontal lines. There are 2 more horizontal lines, which are the buffered and inverted clones of the same wire. This was originated from each OLMCs. There are pins you can use as inputs only. These pins utilize a buffer/inverter stage similarly to the ones just described. These two lines are also connected to the horizontal lines of the matrix. This 3 kind of wires form the rows of the matrix. While the 1st kind of lines cross all the vertical lines, the 2nd and 3rd type wires are shorter and are arranged to complete each other's lengths resulting a diagonal pattern of fixed internal matrix connections. The vertical lines are connected to these internally connected points. This is the description of an empty device. Programming of the device means to join any vertical line to any horizontal wire - if they cross each other. Only crosspoinst can be connected. I hope you have a drawing about the structure at your hand and can follow me, beacause I have limited access to internet via ham radio interface and cannot send files with the only exceptions of text. Well, if you examine a JEDEC file which describes a GAL, it looks like this: TITLE :GATES AUTHOR :RETALLER PATTERN :A COMPANY:EVORAN BT REVISION:1.0 DATE :15/09/93 GAL16V8 GATES* QP20* QF2194* G0*F0* L0000 0000000000000000000000000000000000000000* L0040 0000000000000000000000000000000000000000* L0080 0000000000000000000000000000000000000000* L0120 0000000000000000000000000000000000000000* L0160 0000000000000000000000000000000000000000* L0200 0000000000000000000000000000000000000000* L0240 0000000000000000000000000000000000000000* L0280 0000000000000000000000000000000000000000* L0320 0011111011111111111111111111111111110101* L0360 0000000000000000000000000000000000000000* L0400 0000000000000000000000000000000000000000* L0440 0000000000000000000000000000000000000000* L0480 0000000000000000000000000000000000000000* L0520 0000000000000000000000000000000000000000* L0560 0000000000000000000000000000000000000000* L0600 0000000000000000000000000000000000000000* L0640 1111111111111111111111111111111111111111* L0680 1110111111111111111011111111111111111111* L0720 0000000000000000000000000000000000000000* . . . . . L2480 0000000000000000000000000000000000000000* L2520 0000000000000000000000000000000000000000* L2560 1100100000110010111110101000001001001010* L2600 0100001001001100100111000000010010100000* L2640 1111111111111111111111111111111111111111* L2680 11111111111111111111111101* C35C5* I don't want to explain here the stucture of a JEDEC file, this is an easy to access standard, just want to show how things correlate. The row starting with L0000 represent the first horizontal wire of the drawing, while the row starting with L0040 represent the second horizontal line and so one. Line L0000 consist of 40 fuses, fuse 0 on leftmost and fuse 39 at rightmost, respectively. Numbering is continued in the next line, i.e. L0040 consist fuses 40...79 in the same manner and more fuses are represented similarly. But be careful and see JEDEC standard, which says, not all the fuses must be described individually. It is possible to handle the question by defining the default value and just mention the fuses, which are not of default. If you defined '0' as default, the file above may start like this: L0322 11111011111111111111111111111111110101* Note, however this is described a bit differently, it is logically the same! Files described this manner, should be converted to the form above to see how individual fuses will be programmed. During programming, GAL's should be handled as shift registers of 40 bits length. Here are the pin descriptions for GAL 16V8 and 20V8: 16V8 20V8 1 VIL VIL 2 EDIT EDIT 3 RAG1 RAG1 4 RAG2 RAG2 5 RAG3 RAG3 6 RAG4 VIL 7 RAG5 VIL 8 SCLK RAG4 9 SDIN RAG5 10 GND SCLK 11 STR SDIN 12 SDOUT GND 13 VIL STR 14 VIL VIL 15 VIL SDOUT 16 VIL VIL 17 VIL VIL 18 RAG0 VIL 19 P/V VIL 20 Vcc VIL 21 RAG0 22 P/V 23 VIL 24 Vcc VIL represents a pin to be kept low level during programming. EDIT pins are used to deliver the programming voltage. It is about 15.5V for Lattice, National Semiconductor and SGS made 16V8B and 20V8B and toward to 'D' signed devices, but depends on manufacturer as well as type. RAG0,...RAGx is used to address different 40bit shift registers, representing lines L0000, L0040, etc. in JEDEC file. RAG equal 0 during programming L0000 line, RAG equal 1 during programming L0040, .... RAG equal 17 during programming L0680. SCLK is the serial data clock. SDIN is the serial data input. SDOUT is the serial data output. P/V is the program/verify switch. Perhaps you have noticed that there are more Lxxxx lines in the JEDEC file than horizontal rows. The plus lines consist of informations about the following things: Signature: 16v8: RAG=32 20v8 RAG=40 The following items are found at the same RAG address at both GALs: Architecture control word: RAG=60 (82 bits wide!) Security bit: RAG=61 (1 bit wide) Reserved, unknown bit RAG=62 (1 bit wide) Bulk erase bit: RAG=63 (1 bit wide) The structure of the architecture control word depends on manufacturers. It controls the connection fuses to be found between the matrix's rows and OLMCs as well as the OLMC's polarity, and the SYNC/ASYNC behavior of OLMC's. Be careful, manufacturers scramble this 82 bits so much that even a single bit can be taken away from other similar bits, and can be inserted to an other place, where other kind of grouped bit order will be destroyed by this bit... Thats all, falks.... Istvan