If you are concerned at all with speed, consider using a ROM.
     TTL Input lines go to address pins of the ROM(s), and outputs come from the
     data pins.  Add three additional address bits to select one of the 8
     possible routings.  Create your eight lookup tables with a formula, load it
     into the ROM.  Only a few nanoseconds delay.

     If pwb area and speed is a concern, use a FPGA.... just one little chip.
     Lattice has some ISP chips that use inexpensive tools.  About $100 for
     programmer and design software.

     A C508 can take care of a pile of parallel-serial and serial-parallel shift
     registers, support is all around, you have the tools onhand, and parts are
     inexpensive.



     ------------------------------------
     I have a project that I have been working on for the better part of forever
     trying to find the "Elegant" solution.

     Basic problem is rerouting a set of TTL signals into a different
     configuration.

     Example

     Source          Dest
     A               B
     B               A
     C               F
     D               E
     E               D
     F               C

     With there being 8 different routings possible.  And 32 (possibly only 16)
     lines being routed at a time.

     What I am wondering is if a PIC would be a good candidate for this task.

     At startup of the pic (or on reset) it would have to find out which of the
     8 routing maps it was currently using (from a 3 bit mode select which is
     then no longer used) and load the relevant routing code.

     Then I envisioned a buffered input latch on the source side that would be
     polled by the pic as a word or dword then tri-stated.  The values of each
     line would then be bitwise transferred into the appropriate dest value
     (d)word bit.  Once all lines are routed the resulting value would then be
     latched into an output buffer for being read by the dest side of the
     system.

     Then it would loop back to the read of the source latch etc.

     Timing on the source side is not hyper critical and if I don't care about
     edges of events on that side.  I think I will be clocked on the dest side
     but I am not sure yet.

     Ideas / comments welcome.

     David