Here's an interrupt entry and exit code for a '74 project:

        CBLOCK  0x20
        rTempW                    ;
        rTempStatus               ;
        rTempPCLATH               ;
        rTempFSR                  ;
        ; .... insert more RAM use declarations ....
        ENDC

        CBLOCK  0xA0
        rTempW2                   ; must also reserve this location to store W
        ; .... insert more RAM use declarations ....
        ENDC


        ORG     4                 ; Interrupt vector
handleInterrupt
        movwf   rTempW            ; save W value (could be in page0 or 1!)
        swapf   STATUS,W          ;
        bcf     STATUS,RP0        ; set RAM page 0
        movwf   rTempStatus       ; save STATUS value
        movfw   PCLATH            ;
        movwf   rTempPCLATH       ; save PCLATH Value
        movfw   FSR               ;
        movwf   rTempFSR          ; save FSR value
        bcf     PCLATH,3          ; set program memory page 0

        ; .... interrupt handling ....

        bcf     STATUS,RP0        ; be sure RAM page 0 is selected
        movfw   rTempFSR          ;
        movwf   FSR               ; restore FSR value
        movfw   rTempPCLATH       ; restore PCLATH Value
        movwf   PCLATH            ;
        swapf   rTempStatus,W     ; restore W and Status
        movwf   STATUS            ;
        swapf   rTempW,F          ;
        swapf   rTempW,W          ;
        retfie                    ; done with interrupt

This requires five RAM locations, and it takes 20 instruction cycles. If at all
possible, avoid calling subroutines and using the FSR in the interrupt handler.
Sometimes you have to take action on an interrupt as quickly as possible -
context saving eats up valuable time.

PIC interrupt handling cannot be interrupted by a subsequent interrupt, so
clearing GIE is not required. I am not familiar with some of instructions in
your code (is it Parallax assembler?), but it appears that when saving your W
register, you could be altering the STATUS,Z bit.

Dave


jhobbs wrote:

> Here is something I have been doing with the 73.
>
> Given that an interupt can occur at any given time, and code execution could
> be taking place on any page and working with any bank.
> What does this mean?
>
> I had found like many others that things with a PIC are not nicely restored
> with a RETI.
> So we all do the status and w thing, no big deal.  But what about rp0 (bank)
> and pclath.3 (page)?
>
> Well, the first thing you do in your ISR is clear rp0, now you are safe to
> do the status and w thing.  But how do you know what  rp0 was before you
> cleared it?  I have heard said, "you can duplicate _copy FR in both banks",
> yuck, and I am tight on space.  What else can I do?
>
> Hey, hold on a sec. my ISR seems like it is all over the place some times.
> I know I have code in page 1 and that the pclath is adjusted appropriately
> for calls, lookups etc.  This definetly can cause problems executing my ISR
> in page 0.  Hmm, now it looks like I need to record and restore pclath as
> well.  Now things are looking ugly.
>
> I need a FR that can be addressed from either bank.  That is where I will
> store rp0 and pclath.3.
>
> Well, this is how I have been doing it.  I use the status register, bits
> 7and 6.
>
> Any comments welcomed, good/bad, does this help anyone?
> **********************************************************************
>
> ;bank = status.7  ;general purpose bit 0=bank 0, 1=bank 1
> ;page = status.6
>  ORG 00H
>  jmp begin
>  org 04h
>
> :loop clrb gie          ;turn off int.
>  jb gie,                     :loop
>
>  snb rp0
>  setb bank                                                ;*Recording the
> status of rp0
>  clrb rp0                  ;set bank 0               ;*Make sure that you
> are accessing the right bank
>
>  mov w_copy,w                                        ;*Doing the status and
> w thing
>  mov s_copy,status
>
>  snb pclath.3
>  setb page                                               ;*Recording the
> status of pclath
>  clrb pclath.3                                            ;*Make sure that
> you are accessing the right page
>
>  <Work your magic here>
>
>  mov status,s_copy
>  swap w_copy
>  mov w,<>w_copy
>
>  snb page
>  setb pclath.3                                            ;restore page
>
>  snb bank
>  setb rp0                                                   ;restore bank
>
>  clrb bank                                                 ;reset bank flag
> DO NOT FORGET
>  clrb page                                                 ;reset page flag
>
>  reti
> **********************************************************************
>
> Take care  -jim