Dennis Plunkett <dennis@RDD.NECA.NEC.COM.AU> wrote:
> Also the FLASH device has 4 gates
> per memory cell, whereas; an EEPROM has 6.

Actually, no.  Maybe you're thinking of SRAM cells; low power CMOS SRAM uses
six transistor cells, and higher density (but higher power) cells use
four transistor cells.

EPROM, EEPROM, and Flash all ususally use one transistor per cell, although
it is an unusual transistor with a second "floating" gate.  For very
high speed memory, Sometimes a second transistor is added, because the same
characteristics that make a good storage transistor also make a relatively
slow switch.

In the past EEPROM cells sometimes had two separate floating gate
transistors for storing ones and zeros, and read the bits using differential
sensing.  In such devices, the erased (or unprogrammed) state was
indeterminate.  This was relatively common in the old MNOS (*) EEPROMs.
However, I don't think this technique is much used any more.

Maybe someone from Microchip would care to comment on how their Flash
technology works?

Cheers,
Eric

(*)  Yes, I really meant MNOS.  Not NMOS.