>It was mentioned, yes.  Someone asked about it and the presenter
>mentioned the SBI (Set bit in IO Reg) and CBI (Clear bit in IO Reg)
>instructions.  These do take 2 clock cycle, though.  So there the PIC
>beats the AVR.  Although, an AVR running at 1/2 the speed of a PIC would
>be able to handle the same rate of IO change as the PIC, courtesy of the
>1-clock-cycle-1-intruction-cycle mechanism.  I really wonder how they did
>that!?!


My experience on high speed bit-banging on the PIC was that at 4 mhz, it
needed
a NOP between bit changes, which adds even more time to it (of course).
I was told that this was because of "high capacitance or load" but all I'm
driving is a single cmos gate at the end of 0.4" if track.

Scoping the lines confirmed that the output bits were occasionally failing
to
change state as ordered, adding the NOPS into the straightline output code
solved the "missing bits"

 The AVR can truly execute sequential bit operations without intervening
nops,
at 8 or 12 mhz.

Don't get me wrong, I'm not a processor bigot, I just use whatever suits the
job.
I do think though, that proponents on both sides have attempted to hide
their
various warts.