Rudy, while I was designing the chip-set I was always concerned about
unforeseen software issues. One of those was the ability to know the
absolute (physical) trigger address. I've looked at several other designs
and some included it. I really did'nt think it was necessary but I added it
in case others might see a benefit. When a `gotcha' cropped up and it looked
like I was going to have to eliminate it or add a `glue' chip, I sought
opinions from the group. Some folks preferred the capability. I was able to
squeeze in some extra logic to cover the `gotcha' so I decided to retain it.
If I removed it, I would free-up 4 I/Os and 1 dedicated input. That may
allow me to fit the external decade clock prescaler in that chip. This would
eliminate 2 74x390s but, internally, that chip's resources are mostly
`exhausted'...

   From a software standpoint, it makes no difference if I keep it. It uses
4 states of a 12-state machine. The first 8 control reading data from the
SRAMs. If you ignore it, your host (PIC or PC) has one less control line to
deal with (3 state-select inputs vs. 4).

   - Tom

At 02:27 PM 4/29/98 +0200, Rudy Wieser wrote:
[snip]
>Tom Handley wrote:
>> I like your suggestion of clocking in 32K and then subracting the delay.
>> Last night I did another update to that particular CPLD and I was able to
>> eliminate 1 74x-family `glue' chip while retaining the capability to read
>> the absolute address. At this point, eliminating the address read-back
>> will not save anything so I'll keep it.
>>
>>    - Tom
>
>Ehh .. Tom, something keeps nagging me :  Why do you need to be able
>to read the absolute adres of the Sample-buffer ?  As you've seen, you
>don't
>really need it (anymore).